Distributed Performance Analysis
Find critical paths and stragglers across ranks
Reconcile utilization and scaling metrics with wall time, align causality across ranks, measure exposed communication and bubbles, and reduce a large-scale regression to a controlled experiment.
Consider a training job that uses 64 devices, where each device is a graphics processing unit (GPU). The job's median step time increased from 410 milliseconds to 485 milliseconds after a software update. One central processing unit (CPU) process controls each GPU. A cluster telemetry service samples NVIDIA Data Center GPU Manager activity for every GPU once per second and publishes a dashboard average of 81 percent. The sampled activity reports that GPU work was present during many sampling intervals, but the cross-device average does not identify the extra 75 milliseconds. One delayed process can make 63 healthy peers wait, so the process that displays the longest wait is not necessarily the process that caused the delay.
The investigation begins by collecting the same steady-state steps on every rank with PyTorch Profiler or Nsight Systems. Each profiler writes timestamped events for CPU operations, CUDA kernels, and supported communication calls. The resulting trace is a timeline record produced during that profiling run. Engineers add step, microbatch, layer, and collective identifiers so events from different process clocks can be matched even when their absolute timestamps are imperfectly synchronized.
A concrete comparison might show ranks 0 through 62 reaching gradient all-reduce number 417 at 360 milliseconds, while rank 63 arrives at 433 milliseconds after an unusually long general matrix multiplication (GEMM). The wide collective bars on the early ranks mostly record waiting for rank 63. The earlier matrix operation on rank 63 is therefore the first unexplained divergence, while the collective wait is a downstream symptom. An NVIDIA Nsight Compute profile of that GEMM can estimate streaming multiprocessor (SM) activity and bytes transferred between high-bandwidth memory (HBM) and the on-chip cache hierarchy. The named Nsight Compute measurements test compute-underuse and HBM-traffic explanations without treating the dashboard average as a cause.
This chapter defines efficiency ratios from explicit numerators and denominators, including estimated model floating-point operations (FLOPs). The chapter also explains how distributed traces are produced and aligned, distinguishes useful overlap from visual overlap, and reduces large-job regressions to controlled experiments. Every calculation must reconcile with measured step time; any remaining interval is labeled unclassified rather than assigned to a convenient cause.
Prerequisites
- Chapter 7 profiler scope and timestamped event records
- Chapters 13–14 communication, topology, and parallel ownership
- Ability to compare distributions and follow a dependency critical path
Learning objectives
- Calculate efficiency rates from recoverable numerators and denominators
- Align rank events and locate the first delay that determines synchronization
- Measure exposed communication, pipeline idle time, and mutual slowdown in controlled runs
Study this chapter
- 15.1Distributed efficiency metricsBegin lesson →
Reconstruct model FLOP utilization and scaling efficiency from declared work, elapsed seconds, hardware count, datatype peak, and shape assumptions
- 15.2Cross-rank trace alignmentBegin lesson →
Align ranks by logical step and collective identifiers, separate arrival skew from remaining transfer, and locate the first material divergence
- 15.3Overlap, exposed communication, and bubblesBegin lesson →
Measure readiness, completion, first consumption, exposed tail, concurrent-kernel slowdown, and peak memory for one overlap change
- 15.4Distributed diagnosis processBegin lesson →
Reduce a large-scale regression through one-rank, one-node, two-node, and full-scale tests while preserving the mechanism that distinguishes the hypotheses
Extended exercises
Complete these projects after the lesson-level practice tasks. Each project combines several mechanisms from the chapter.
Metric audit
Compute valid tokens per second, model FLOP utilization, and strong-scaling efficiency for one declared training run.
Evidence: A reproducible calculation stating valid and padded work, arithmetic convention, datatype peak, device count, synchronization boundary, and measured step distribution.
Synthetic straggler
Inject a known 15-millisecond delay before one collective on one rank and capture at least ten steady-state steps on all ranks.
Evidence: Aligned timestamped events that identify the injected rank, readiness spread, downstream peer waits, and recovered 15-millisecond causal path.
Parallelism ablation
Sweep one parallel degree while holding global useful work, model semantics, and hardware placement policy fixed.
Evidence: Local shapes, peak memory, message bytes, rank-arrival distributions, complete step time, and one observation that explains the crossover.
Sources and further reading
The lesson explanations synthesize primary papers and official references. Follow the originals for proofs, exact APIs, architecture details, and version-sensitive behavior.