IIntroduction to AI Systems Performance EngineeringTechnical textbook
Chapter 1

Performance Models and Metrics

Calculate what arithmetic, data transfer, dependencies, and waiting predict about elapsed time

Use units and four small models to predict a GPU program's minimum execution time, how much a faster GPU interval reduces complete request latency, queue growth under load, and the rate permitted by HBM traffic.

Run one language-model request while NVIDIA Nsight Systems records the activity of the host central processing unit (CPU) and graphics processing unit (GPU). Nsight Systems produces a time-ordered file in which every recorded row has a start time, an end time, and a label such as a Python operation, a CUDA kernel launch, or a memory copy. Engineers call this timestamped event record a profiler trace. A ten-second recording can contain thousands of rows because one generated answer can launch many GPU programs for every output token.

A long event list does not explain the delay by itself. Suppose the trace shows a 1.8-millisecond matrix-multiplication kernel and a 0.4-millisecond normalization kernel. The useful questions are quantitative: How many numerical operations did each GPU program have to perform? How many bytes traveled from the GPU's high-bandwidth memory into on-chip caches? Which recorded intervals lie on the chain of dependencies that determines request latency? How many admitted requests were waiting while the GPU completed 600 requests per second? Each question names an amount, a unit, and a relationship that can make a testable prediction.

The first lesson connects an amount of arithmetic or transferred data to the rate at which named hardware completes that work. The arithmetic unit is a floating-point operation (FLOP). A later example counts the repeated multiply-and-add work in general matrix multiplication (GEMM), written as `C = A × B`.

The second lesson asks how much a shorter GPU interval can reduce the complete request. Amdahl's law supplies the calculation, while a dependency timeline shows whether the shortened interval lies on the request's critical path.

The third lesson connects admitted requests, completed requests per second, and time spent inside named server entry and exit events. The fourth lesson compares arithmetic work with bytes transferred between GPU high-bandwidth memory and the on-chip cache hierarchy. Each model omits details on purpose; later measurements test whether the omitted details matter for the workload under investigation.

Prerequisites

Learning objectives

  • Carry operations, bytes, seconds, and rates through a calculation without losing their meaning
  • Use Amdahl’s law and Little’s law with named timing and service boundaries
  • Build a roofline prediction from a declared GPU instruction path and HBM-to-cache traffic
Lessons

Study this chapter

  1. 1.1
    Units, work, and rates

    Estimate arithmetic work and HBM-to-cache bytes for a declared tensor operation before profiling

    Begin lesson →
  2. 1.2
    Parallel speedup and critical paths

    Predict the largest request-latency reduction available from shortening one recorded GPU interval

    Begin lesson →
  3. 1.3
    Queueing, saturation, and Little’s law

    Connect concurrency, throughput, and latency

    Begin lesson →
  4. 1.4
    Roofline performance model

    Classify a kernel as bandwidth- or compute-limited

    Begin lesson →
Chapter projects

Extended exercises

Complete these projects after the lesson-level practice tasks. Each project combines several mechanisms from the chapter.

01
Check

Transformer arithmetic

For one declared dense-layer shape and datatype, estimate floating-point operations and the minimum bytes read for weights and activations and written for output.

Evidence: A dimensional calculation that names every tensor axis, counts bytes per element, and preserves units through the final result.

02
Practice

Roofline worksheet

Model vector addition, reduction, and square general matrix multiplication on one documented GPU. Name the HBM-to-cache interface and instruction path used for each ceiling.

Evidence: A table of operation counts, byte counts, arithmetic intensities, predicted lower-bound times, and ridge point assumptions.

03
Challenge

Validate one prediction

Benchmark one operation, capture the relevant HBM traffic with a profiler, and compare measured time with both arithmetic and transfer lower bounds.

Evidence: Raw timings, saved profiler report, calculation, and a written explanation of the largest gap between prediction and observation.

References

Sources and further reading

The lesson explanations synthesize primary papers and official references. Follow the originals for proofs, exact APIs, architecture details, and version-sensitive behavior.

  1. Amdahl, Validity of the Single Processor Approach to Achieving Large Scale Computing Capabilities
  2. Little, A Proof for the Queuing Formula: L = λW
  3. Roofline: An Insightful Visual Performance Model
  4. NVIDIA Nsight Systems User Guide

    Official reference for capturing and reading CPU, CUDA API, GPU workload, and communication timelines.

  5. Nsight Compute Profiling Guide
  6. MLPerf Training Benchmark